Paperback: 479 pages
Publisher: Newnes; 2 edition (December 23, 2009)
Product Dimensions: 9.1 x 7.4 x 1 inches
Shipping Weight: 1.6 pounds
Average Customer Review: 3.6 out of 5 stars See all reviews (10 customer reviews)
Best Sellers Rank: #1,170,144 in Books (See Top 100 in Books) #127 in Books > Computers & Technology > Hardware & DIY > Microprocessors & System Design > Embedded Systems #316 in Books > Engineering & Transportation > Engineering > Electrical & Electronics > Electronics > Microelectronics #816 in Books > Computers & Technology > Hardware & DIY > Personal Computers
Despite other critical reviews, I bought the book and enjoyed reading it from beginning to end.I found it pretty informative. The book attempts to be a thorough exposition of the ARM Cortex-M3 from several perspectives: features, instruction set, usage scenarios and best practices. The book goes into a lot of detail on certain aspects such as the interrupt table setup and associated semantics. The book has a mixture of assembly and C examples, with occasional remarks on performance and code size. Finally, despite other reviewers, I enjoyed the comparisons with Cortex-M0, previous architectures (ARM7TDMI) plus porting considerations.The book does feel a bit repetitive in a few places such as the overlapping content on NVIC and its registers, interrupt table format, initialization, dynamic prioritization and enable/disable which is repeated across the book. The exposition on the instruction set could have been done better. Also in several occasions, the author's style was a bit cryptic and I felt that he didn't go far enough in clarity (for example in explaining certain instructions, or in 12.6 FAULTMASK explanation - what is its parameter? Usage cases?). I also noticed a few typos, but these are rather rare.Hence four stars instead of five. I still gave four stars as I still feel that the book feels solid and well-written overall.For the next edition, I would suggest the author to revise the clarity of some of its expository text (give some reason on the "why" not just "how") maybe attempt to eliminate the redundancy, and, of course, the necessary mention of Cortex-M4 (which is not that different than M3) and possibly add comparisons with M0+ which borrows a few things from M3P.S.
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